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Cypress Semiconductor /psoc63 /BLE /BLESS /MT_DELAY_CFG

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Interpret as MT_DELAY_CFG

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0HVLDO_STARTUP_DELAY 0ISOLATE_DEASSERT_DELAY 0ACT_TO_SWITCH_DELAY 0HVLDO_DISABLE_DELAY

Description

MT Delay configuration for state transitions

Fields

HVLDO_STARTUP_DELAY

This register specifies the startup delay for the HVLDO interms of number of LF Clock cycles. FW has to program this register based on the selected LF clock frequency
ISOLATE_DEASSERT_DELAY

This register specifies the time from switching the CYBLERD55 logic to Active regulator to removal of ISOLATE_N
ACT_TO_SWITCH_DELAY

This register specifies the time from assertion of ISOLATE_N to switching the CYBLERD55 logic to Retention LDO
HVLDO_DISABLE_DELAY

This register specifies the time from disabling XTAL to switching of the HVLDO.

Links

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Register License

Copyright 2016-2018 Cypress Semiconductor Corporation \n Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.
You may obtain a copy of the License at \n
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and
limitations under the License.

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data